Description

GE General Electric Technical Specifications: IS200SRLYH2AAA

The IS200SRLYH2AAA MDX-UMC isa universal memory card for the STD Bus.

The MDX-UMC provides the user with the capability of

configuring the board to meet the system requirements of

ROM/EPROM and/or RAM. By the use of strapping

options, the user is able to IS200SRLYH2AAA configure pairs of sockets for

ROM/EPROM/RAM to form a combination memory board.

Other MDX-UMC features include 4K boundary addressing

and an optional wait-state IS200SRLYH2AAA generator to accommodate

slower memories for 4 MHz system clock operations. A

block diagram for the MDX-UMC is shown in Figure 2.

brand	Product Name	Product model	Order No
GE Fanuc	Module card	IS200SRLYH2AAA	nothing
Place of Origin	Marketable land	Imported or not	defects liability period
Europe and America	Nationwide and overseas	yes	a year
Place of shipment	Delivery method	How to use	Applicable industries
Xiamen	Shunfeng Express	Commissioning and installation	Power Plant Steel Plant Cement Plant Shipboard Papermaking
Service advantages	Foreign import, goods preparation and supply	Reasonable price and reliable quality	Pictures are for reference only
Product features	Primary source of goods, supply by model	After sales guarantee	Chen 1810693-7731

The IS200SRLYH2AAA memory array consists of up to 8 RAM, EPROM, or

ROM memories. The memories are organized into an array

of eight devices with each device contributing one byte to an

addressable location.

IS200SRLYH2AAA MEMORY DECODE AND CONTROL

The memory decode and control section is responsible for

generating the necessary chip select and output enable

signals for the memory arrays. Timing within the memory

decode and control section is derived from the STD-Z80 Bus

control signals /MEMRQ, /RD, /WR, and /CLOCK.

The address buffer is responsible for isolating the STD-Z80

address bus from the memory array.

DATA BUFFER

The data buffer isolates the memory array from the data bus

and is controlled by the memory decode and control section.

MEMORY DEVICE SELECTION JUMPERS

Figure 3 shows how J1-J8 are configured to accommodate

the various RAMs, EPROMs, and ROMs.

Table 1 shows how the jumpers J1-J8 are related to

memory sockets. It is important to note that the memory

sockets are configured in pairs for a particular memory

device.

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GE IS200SRLYH2AAA Speedtronic series

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