Description

GE General Electric Technical Specifications: IS200TSVOH1A

This IS200TSVOH1A board is available with 128 or 256 MByte of onboard Reflective Memory

SDRAM. The SDRAM starts at the location specified in Base Address Register 3.

Unlike the previous versions of Reflective Memory products, the RFM Control

and Status Registers do NOT replace the first $40 locations of RAM. The offset

address range is $0 to $7FFFFFF for the 128 MByte and $0 to $FFFFFFF for the

256 MByte option.

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GE Fanuc	Module card	IS200TSVOH1A	nothing
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Europe and America	Nationwide and overseas	yes	a year
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The IS200TSVOH1A has a single interrupt output (INTA#). One or more events on the

IS200TSVOH1A board can cause the interrupt. The sources of the interrupt can be

individually enabled and monitored through several registers.

The interrupt circuitry of the RFM‐5565 is arranged in two tiers. The primary tier

of interrupts is enabled and monitored by the Local Configuration Register’s

INTCSR at offset $68. The sources for monitoring the primary tier interrupts

include:

DMA Ch 0 Done
Local Interrupt Input (LINTi#)

The primary tier interrupt source (1) is used during DMA cycles and must be

configured in the DMA registers.

The IS200TSVOH1A other primary tier interrupt source (2) is the Local Interrupt Input (LINTi#).

All secondary tier interrupts are funneled through the LINTi#. Second tier

interrupts include several operational status bits, faults, and network interrupts.

The second tier interrupts are selected and monitored through the two RFM

Control and Status Registers referred to as the Local Interrupt Status Register

(LISR) and the Local Interrupt Enable Register (LIER). For a detailed description

of these two registers refer to Chapter 3, Programming, on page 31. A block

diagram of the main interrupt circuitry is shown in Figure 2‐1 on page 28.

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GE IS200TSVOH1A IS200TSVOH1B Power card

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