GE IP-Quadrature Four channel orthogonal encoder

Description

IP-Quadrature consists of the following functional blocks:
• Input Circuitry
• Polarity and Function Selection
• Counters
• Interrupt Logic
• IP Interface Logic

There are four quadrature decoder channels on the IP. The channels are independent, although
some input termination options are implemented in groups of two channels.
Each channel has three inputs, called X, Y, and Z. Normally X and Y are the two quadrature inputs
and Z is the optional control or index input. If the channel is used as a general purpose counter then
there are more programmable options for the use of X, Y and Z.
Each channel has its own 24-bit count register, 24-bit preset/comparitor register and 24-bit output
latch register, and its own control and status registers.

The interrupt logic, polarity and function select logic, and IP interface logic is all located in a single
100-pin Xilinx programmable logic cell array (LCA). There are separate registers in the Xilinx LCA
for each channel. These registers select the input polarities, counting functions, and interrupt control
for the four channels.

Input Circuitry
A detail diagram of the input circuit is shown in Figure 3 on the next page. The input circuitry
consists of RS-422 differential receivers (comparitors) with resistors to implement termination
options. Standard input is differential RS-422, terminated with 120? across the input. The
termination resistors are socketed and may be removed or changed by the user. The resistor
designators in Figure 3 are for reference here only; they do not correspond to designators on the
actual IP.

Alternatively the input may be TTL or similar logic levels. One side of the RS-422 input is biased at
approximately 1.75 volts, permitting single-ended TTL, NMOS, CMOS, or opto-coupler input to be
directly connected. When running in this mode, one volt of hysteresis is implemented on the
receiver to reduce noise.

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