0190-23497 Industrial Parts – Supply

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0190-23497 Industrial Parts – Supply

0190-23497 Industrial Parts – Supply

After 28 nanometers, the planar transistor process reached its limit, and FinFET (finned transistor) continued Moore’s law, pushing the process node to below the current 10 nanometers. However, the FinFET route is also approaching its limit, and Samsung will take the lead in adopting a GAA (full surround gate) structure in the 3-nanometer process. TSMC will continue to use the FinFET structure at the 3-nanometer node and then adopt the GAA structure at the 2-nanometer node. The Taiwan Institute of Industry and Technology believes that Intel has encountered difficulties in wafer manufacturing, and the 7-nanometer process (note: the three companies have different definitions of process size, which is not suitable for direct numerical comparison) may be postponed to mass production in 2023. It is expected that Intel will also switch to GAA architecture at the 5-nanometer node.

GAA, also known as Gate All Around, is a type of surround gate technology transistor, also known as GAAFET. The concept was first proposed by Dr. IMEC Cor Claeys and his research team in Belgium in an article published in 1990. GAAFET is equivalent to an improved version of 3D FinFET, and the transistor structure under this technology has changed again. The gate and drain are no longer like fins, but instead become “small sticks” that pass vertically through the gate, allowing the gate to wrap around the source and drain on all four sides.
Compared to FinFET, the original source drain semiconductor was a fin, but now the gate has become a fin. So there are many similarities in the implementation principles and ideas between GAAFET and 3D FinFET – which is a great advantage for wafer factories. From three contact surfaces to four contact surfaces, and also split into several four contact surfaces, it is obvious that the control force of the gate on the current has further improved.

Compared to the FinFET process, the GAA structure has a larger gate contact area, which enhances the transistor’s control ability over conductive channels and significantly improves parasitic parameters such as capacitance. Therefore, it can reduce operating voltage, leakage current, power consumption, and operating temperature, which is beneficial for improving integration and continuing Moore’s law.
Due to the similarity of the production process required by the new structure to the fin transistor, the key process steps are almost the same, and existing equipment and technological achievements can continue to be used. For TSMC and Samsung, this is undoubtedly the lowest cost technology route replacement solution. However, GAA’s requirements for processing accuracy have further improved, requiring regional selective deposition technology and atomic level processing capabilities. As a result, the importance of material engineering has increased, which will also drive more opportunities for deposition and etching equipment.

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