Bently Nevada 3500/92 Communication Gateway Ethernet/set

Description

3500/92 The procedures for verifying channel values and corner frequencies require that

you use the following formulas to calculate the verification frequency:

Find the center of the Band-pass frequency range. Input the configured High

pass Filter Corner Frequency and the Low-pass Filter 3500/92 Corner Frequency into the

formula below:

Vibration Frequency = (0.89 × HPF) + (0.1575 × LPF)

HPF = High-pass Filter Corner Frequency

LPF = Low-pass Filter Corner Frequency

If no filtering is configured, set the frequency of the function generator to 100 Hz.

If a Low-pass Filter is configured and no High-pass Filter is configured, use the

following to determine the HPF to use in the formula:

– If the units are RMS, use a HPF of 10 Hz. For any other configuration, use a

HPF of 3 Hz.

3500/92 If a High-pass Filter is configured and no Low-pass Filter is configured, use a

LPF of 5,500 Hz.

3500/92 The procedures for verifying channel values and corner frequencies require that

you use the following formulas to calculate the input voltage for Full-scale. To

find the Full-scale input voltage, use appropriate table or formula for integrated or

non-integrated units.

3500/92 For Seismoprobes:

The general approach for testing OK limit is to disconnect the input. This will

cause a not OK condition and the OK Relay to change state (de-energize).

1. Run the Verification Software as described in Section 5.1.8.1 (Test

Equipment and Software Setup – Velocity).

2. Disconnect the SIG / A field wiring from the channel terminals on the

Proximitor / Seismic Monitor I/O Module.

3. Verify that the OK relay changes state (de-energized).
4. Verify that the Channel OK State line on the Verification screen reads not
5. OK.
6. Reconnect the SIG / A field wiring to 3500/92 the channel terminals on the Monitor I/O

Module. Press the RESET switch on the Rack Interface Module (RIM) and

verify that the OK LED comes on and the OK relay energizes.

6. Verify that the Channel OK State line on the Verification screen reads OK.
7. If you can not verify any configured OK limit, go to Section 5.1.11 (If a

Channel Fails a Verification Test).

8. Repeat steps 1 through 7 for all configured channels.

3500/92 For Velomitors with Standard I/O Modules:

The general approach for testing OK limits is to input a DC voltage and adjust it

above the Upper OK limit and below the Lower OK limit. This will cause a not

OK condition and the OK Relay to change state (de-energize). The Upper and

Lower OK limits are displayed in the Verification screen on the test computer.

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