DELTA TAU ACC-36E Input/Output Module Conversion Board

The hardware Phase clock period (frequency) is controlled by jumpers E98 and E29-E33 on a Turbo ACC-36E(1), variables I7000 and I7001 on a Turbo ACC-36E that is not Ultralite, or variables I6800 and I6801 on a Turbo ACC-36E Ultralite. Most Turbo ACC-36E users will leave I7 at the default value of 0, so that phase update algorithms are executed every phase clock cycle. There are two reasons to extend the phase update cycle by setting I7 greater than 0. First, if the Turbo ACC-36E is doing direct PWM control of motors over the MACRO ring, it is advisable to set I7 to 1 so that the MACRO ring, which operates on the hardware phase clock, cycles twice per software phase cycle.

This will eliminate one phase cycle delay in the closing of the current loops, which permits higher gains and higher performance. For example, the hardware phase clock could be set to 18 kHz, but with I7=1, the current loop would be closed at a reasonable 9 kHz. Second, if many multiplexed A/D converters from the on-board Option 12, or ACC-36 boards, are used for servo feedback, I7 can be set greater than zero to ensure that each A/D converter is processed once per servo cycle. One pair of multiplexed ADCs is processed each hardware phase clock cycle. For example, if 8 pairs of multiplexed ADCs needed to be processed each 440 µsec (2.25 kHz) servo cycle, and the software phase update were desired to be at 220 µsec (4.5 kHz), the phase clock update would be set to 18 kHz (18/8 = 2.25) to get through all 8 ADC pairs each servo cycle, I7 would be set to 3 (18/[3+1] = 4.5) to get the software phase update at 4.5 kHz, and the servo cycle clock divider would be set to divide-by-8 (E3-E6 on Turbo PMAC(1), I7002=7 on non-Ultralite Turbo PMAC2, I6802=7 on Turbo PMAC2 Ultralite).

There must be an integer number of software phase updates in a Servo clock period. For example if the Servo clock frequency is ¼ the Phase clock frequency (I7002 or I6802 = 3), the legitimate values of I7 are 0, which provides 4 software phase updates per servo clock period; 1, which provides 2 updates per period; and 3, which provides 1 update per period. Note that this rule means that the software phase update period must never be longer than the servo clock period.