Description
GE General Electric Technical Specifications: IS200JGNDG1A
The level of access to the IS200JGNDG1A SASI is determined by the state of.
the U/S bit in the CSR register. When the U/S bit is ‘0’, only
the supervisor may access the SASI. When the U/S bit is
‘1 ” both the user and supervisor may access the SASI.
When both the user and supervisor are allowed access, the
mode of the DMA operation is the IS200JGNDG1A same as the mode of the
master that programmed the SASI to do the DMA operation.
That is, if the SASI is programmed in the user mode to do a
DMA transfer, then the address modifier code used for the
DMA transfer will be a user code. If the SASI is programmed
in the supervisor mode, the address modifier codes for the
DMA will be a supervisory code.
brand | Product Name | Product model | Order No |
GE Fanuc | Module card | IS200JGNDG1A | nothing |
Place of Origin | Marketable land | Imported or not | defects liability period |
Europe and America | Nationwide and overseas | yes | a year |
Place of shipment | Delivery method | How to use | Applicable industries |
Xiamen | Shunfeng Express | Commissioning and installation | Power Plant Steel Plant Cement Plant Shipboard Papermaking |
Service advantages | Foreign import, goods preparation and supply | Reasonable price and reliable quality | Pictures are for reference only |
Product features | Primary source of goods, supply by model | After sales guarantee | Chen 1810693-7731 |
The SASI provides a diagnostic test mode which allows the
SASI to test the SASI IS200JGNDG1A interface and perform DMA
operations without a controller connected. The test mode
should be used only when the controller is disconnected.
When the TEST ENABLE bit in the CSR is set high, the test
mode is selected and the SASI signals are controlled as
follows:
REQ* -‘
BSY*-
1/0-
C/O –
MSG* –
RESET* –
ACK* is connected to REQ*
SEL* and TBSY are logically or’ed and inverted
and then connected to BSY*
R/W is connected to I/O
TC/D is inverted and then connected to C/O
TMSG is inverted and then connected to MSG*
RESET* is controlled normally through the CSR
register. The RESEP signal itself is read through
the DMA STATUS register.
.
When the TEST ENABLE bit is selected, a DMA read or write
transfer may be performed by setting the SASI signals to the
proper state and then IS200JGNDG1A enabling the DMA. Since the SASI
data bus is not connected to anything, all ‘O’s will be written
into write DMA’s. During read DMA’s, the data at the SASI
bus ry during is’ going out and cannot be checked.
This test mode allows the user to verify most of the DMA
master logic used during an actual DMA operation.
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