GE IS200JPDDG1A POWER SUPPLY BOARD

Description

GE General Electric Technical Specifications: IS200JPDDG1A

The VME-MMCPU is a state-of-the-art, high density

processing element which includes a 68000 processor, a

68451 Memory Management Unit(MMU), and 128K bytes

of read-write memory. The IS200JPDDG1A DRAM subsystem includes byte

parity checking, and can be programmed to be accessible to

privileged external masters on the VMEbus. The base

address of DRAM on the VMEbus can also be programmed

to start at any multiple of 4K bytes.

The MMU IS200JPDDG1A stands between the 68000 and all on-board and

off-board elements of the system, providing address

mapping and access privilege checking on all cycles. The

MMU “completes” the architecture of the 68000 by

providing a meaningful distinction between the Supervisor

(operating system) and User (application) modes of

operation, as well as allowing a distinction between Code

(program) and Data address spaces and segments. Use of a

Memory Management facility is essential to prevent inter-

system integrity and thorough checkout of modular

software even in dedicated multi-tasking among co

operative programs.

Several features of the MMCPU enhance its applical;>ility to

multi-processor IS200JPDDG1A systems: the MMU facility, the VMEbus

accessibility of on-board ,RAM at a programmable base

address, and the fact that the MMCPU does not request or

use the VMEbus.except as necessary. Once it has acquired

use of the VMEbus, the MI\iICPU will retain VMEbus control

if no other master is requesting the bus, thereby improving

performance for subsequent cycles on the VMEbus.

Performance in a multi-master or multi-processor system is

further enhanced by the fact that the MMCPU will release

the Bus Busy signal during a cycle on the VMEbus, allowing

overlap of arbitration for the next master with the current

data transfer cycle by the MMCPU.

The. MMCPU design includes provIsion for future

expansibility in several areas to provide the user with a

product with compatible growth potential .as future LSI and

VLSI devices become available. The design includes

provision for the following types of expansion:

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Lead time problem
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