GE IS200JPDFG1A DC INPUT 94V-0 PDM

Description

GE General Electric Technical Specifications: IS200JPDFG1A

Interrupt IS200JPDFG1A Acknowledge (Tri-state, output, active low). The INTAK*

signal indicates that an interrupt acknowledge cycle is in

progress, and the interrupting device should place its response

vector on the data bus. The INTAK* signal is equivalent to an

10RQ* during an M1 *.

44

INTRQ*

IS200JPDFG1A Interrupt Request (Input, active low). The Interrupt Request

signal is generated by 1/0 devices. A request will be honored at

the end of the current instruction if the internal software

controlled interrupt enable flip flop (IFF) is enabled and if the

BUSRQ* signal is not active. When the CPU accepts the

interrupt, an interrupt acknowledge signallNTAK* (lORQ* during

an M1 *) is sent out at the beginning of the next instruction

IS200JPDFG1A CPU that the addressed memory or 1/0 device is not ready for a

data transfer. The CPU continues to enter wait states for as long

as this signal is active. This signal allows memory or 1/0 devices

of any speed to be synchronized to the CPU. Use of this signal

postpones refresh as long as it is held active.

46

NMIRQ*

Non-Maskable Interrupt Request (Input, negative edge triggered).

The Non-Maskable Interrupt Request line has a higher priority

than the INTRQ* line and is always recognized at the end of the

current instruction, independent of the status of the interrupt

enable flip-flop. NMIRQ* automatically forces the CPU to restart

to location 0066H. The program counter is saved automatically

in the external stack so that the user can return to the program

that was interrupted. Note that continuous WAIT cycles can

prevent the current instruction from ending, and that a BUSRQ*

will override a NMIRQ*.

47

SYSRESET*

System Reset (Output, active low). The System Reset line

indicates that a reset has been generated either from an external

reset or the power on reset circuit. The system reset will occur

only once per reset request and will be approximately 2us in

duration. A system reset will also force the CPU program

counter to zero, disable interrupts, set the I register to OOH, set

the R register to OOH, and set Interrupt Mode O.

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