IS200KSPAH1BAA MARK VI GE HS SIG PROC DAUGHTER

Description

GE General Electric Technical Specifications: IS200KSPAH1BAA

All lines going onto or off of the board are TTL buffered

and/or terminated. The IS200KSPAH1BAA data bus lines are bidirectional so

that data can go in two directions. The direction of the data

bus buffer is controlled by the CPU, so that the data bus

buffer will always be enabled out when the CPU is

accessing on board memory or the CTC. The data bus buffer

will be enabled pointing IS200KSPAH1BAA onto the CPU card when an off

board memory, 110, or interrupt vector is addressed. The

data bus buffer will go to a high impedance whenever a

bus-acknowledge signal is issued from the CPU. The

address and control lines are unidirectional buffers and will

go to a high impedance level whenever a bus acknowledge

signal is issued by the CPU.

The IS200KSPAH1BAA wait state circuitry was added to allow 4 MHz operation

with standard memory and standard 1/0 devices. When the

wait state circuit is enabled as shown in Table 4, one wait

state is inserted in the current timing sequence, either in

memory access or 1/0 operation. Refer to. the CPU

(MK3880) section of the IS200KSPAH1BAA manual for wait state timing. The

wait state circuitry is normally. not enabled for 2.5 MHz

operation.

Jumper pins, labeled E7 Pins 1-4 have been provided to

allow the Memory Expansion and 110 Expansion lines to be

tied to ground. This option can be implemented by

jumpering these pins as shown in Table 5.

Both assemblies have the same physical placement of the

strapping options. Figure 3 does denote the difference in the

numbering scheme used for each assembly. Please note

that only the numbering ofthe headers have been changed

and not the routing of the signals to the headers.

Figure 4 further illustrates the difference in these two

assemblies designators.

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