GE IS200SPIDG1ABA Accessory ID Terminal Board

Description

GE General Electric Technical Specifications: IS200SPIDG1ABA

All IS200SPIDG1ABA DIGITAL I/O BUS lines are transmitted over balanced

differential, twisted pair lines with provisions for term

ination resistors at each end of the bus. This method

ensures adequate noise immunity in industrial environ

ments. A 40-pin latching IS200SPIDG1ABA type connector is used to provide

positive locking to the DIGITAL I/O BUS. A 40-conductor,

twisted-pair, flat cable is used to interconnect DIOP and

other DIGITAL I/O BUS peripherals to DIOB1. The bus

receivers are equipped with a fail-safe operation which will

reset all data and data direction registers should the bus

cable be interrupted. The data read by the CPU, however,

will be FF. Figure 5 and Figure 6 show the bus

configurations for the signals on the DIGITAL I/O BUS.

WARNING:lf resistor termination packages are located on

more than one DIOP on the same DIGITAL I/O BUS,

damage to the bus drivers will result.

A4-Al selects which DIOP unit on the DIGITAL I/O BUS

IS200SPIDG1ABA communicates with DIOB1. Each DIOP compares these

four address signals to on-board strapping options to

generate its address enable signal. AO is used to select the

II

left (AO low) or right (AO high) relay port on the selected

DIOPduring a read or write cycle. A5 is used to select a data

(A5 low) or data direction (A5 high) register on the selected

DIOP during a write cycle. Table 5 shows the address bit

patterns (A5-AO) used to select the ports in a system

containing 16 DIOP units.

Control Signals

CRD and CWR are the coded control signals. On receipt of a

CRD command, the relay port selected by A4-AO will place

its data on D7-DO ofthe DIGITALI/O BUS, and hold itthere

until CRD is released. A5 is a “don’t care” signal during a

read cycle. On receipt of a CWR command, the data or data

direction register selected by A5-AD will capture the data on

D7 -DO ofthe DIGITAL I/O BUS atthetrailing edge of CWR.

The coincidence of CRD and CWR both active constitutes a

reset condition which clears the data and data direction

registers on all DIGITAL I/O BUS peripherals. The data

direction registers are write only registers and should be set

by the restart or power-up routine software. The data

registers should be used to manipulate the output data

during normal program execution.

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