IS200STCIH1ADD GE DIN RAIL CONTACT INPUT CARD

Description

GE General Electric Technical Specifications: IS200STCIH1ADD

The IS200STCIH1ADD MDX-INT also provides internal interrupt expansion

Figure 2

through a concept of System Interrupt Units (SIU). The

interrupt system ofthe STD-ZSO compatible CPUs will allow

up to five System Interrupt Units without need of expansion.

The MDX-INT has IS200STCIH1ADD circuitry to allow expansion of board with

up to 40 SIUs. It must be the last card (the lowest priority) in

the interrupt daisy chain. An SIU is defined as an interval of

PCI

lEO

time equivalent to the worst-case propagation delay of the

priority daisy chain IS200STCIH1ADD through an MD board. A board with one

interrupting peripheral component, such as an MDX-SIO,

has one SIU. A board with two interrupting peripheral

components, such as an MDX-PIO, has two SIUs. A board

PCO

with no interrupt capability has zerO SIUs.

The Op-Code Prefix Decoder searches the data bus for two

things: an ED two-byte instruction, and an RETI instruction.

When an IS200STCIH1ADD ED two-byte instruction is decoded, a WAIT state

is inserted. Next the data is inspected for a 4D, the second

part of the RETI. If a 4D is present, additional WAIT states

are added corresponding to the number of SIUs selected. If

not, no additional wait states are added.

WAIT State Sequencer

This IS200STCIH1ADD micro-programmed sequencer is a state controller

designed to add wait states in conjunction with the op-code

prefix decoder. It allows the decode of a RETI (ED-4D)

instruction and the propagation of a correct PCI to all boards

in the system. If WAIT states are not required, the interrupt

expansion capability can be disabled by removing jumper

E2. This prohibits WAIT states from being introduced on the

bus.

CTC

The MK3882 is a flexible zao peripheral that allows

operation as either a counter or timer on to 4 channels. The

outputs of the CTC are buffered and wired to connector J2.

The outputs are the ZCITO from channels 0 through 2.

Clock and Trigger inputs are buffered and provided for all

four channels.

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