GE IS200STCIS6A DIN RAIL CONTACT INP

Description

GE General Electric Technical Specifications: IS200STCIS6A

The board consists of nine main elements: address buffers,

address/bus control decode logic, bi-directional data

buffers, power detect circuitry, backup batteries, clock

control register, clock data latches, CMOS clock circuit. and

clock set logic. The address/bus control decode logic

controls the direction of the bi-directional data buffers and

the enabling of the IS200STCIS6A clock control register, data clock latches,

and the clock set logic. The power detect circuitry detects

system power failure and prevents the TTL from interacting

with the battery-backed-up CMOS. The clock control

register selects the desired IS200STCIS6A operation of the CMOS clock

circuit (i.e., read seconds, set seconds, read minutes, and so

on). The clock data latches, in conjunction with the clock

control register, enable and select the desired clock data

(seconds, minutes, hours, day of the month, and month).

The CMOS clock circuit is a battery-backed-up clock which

retains data for five days on fully charged batteries. The

clock set logic allows clock setting through the STD BUS

interface.

The IS200STCIS6A MDX-BCLK module port address block permits port

selection and system flexibility. Address selection is

accomplished by installing the proper straps on Header J5.

Installing a strap is equivalent to selecting the particular

address bit to zero. In addition, the board can only be port

addressed on even bit increments (i.e., DOH, 02H, 04H … ).

Figure 3 is an example of a port addressed at 80 H.

External Clock Input

Header J3 is provided to input a clock frequency other than

the on-board 1 Hz frequency and is primarily intended for

testing purposes. Header J3 must be strapped for module

functional capability, and is strapped before shipment.

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Lead time problem
(1) For the spot products in stock, the de

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