Description
GE General Electric Technical Specifications: IS200TSVCH1A
The status LED’s power up default state is ON. The status LED is a user defined
board indicator and can be toggled ON or OFF by writing to Bit 31 of the Control
IS200TSVCH1A and Status register. The signal detect LED turns ON if the receiver detects light
and can be used as a simple method of checking that the optical network is
properly connected to the receiver. The Own Data LED is turned ON when the
IS200TSVCH1A board detects its own data returning over the network. The default setting is OFF.
The following sections describe the functionality of the RFM‐5565 Reflective
Memory board. A description of the major sub‐circuits and their operation is
included. This section will also occasionally mention Control and Status registers
related to operations. To see a detailed description of these Control and Status
registers please refer to Chapter 3, Programming, on page 31 of this manual.
brand | Product Name | Product model | Order No |
GE Fanuc | Module card | IS200TSVCH1A | nothing |
Place of Origin | Marketable land | Imported or not | defects liability period |
Europe and America | Nationwide and overseas | yes | a year |
Place of shipment | Delivery method | How to use | Applicable industries |
Xiamen | Shunfeng Express | Commissioning and installation | Power Plant Steel Plant Cement Plant Shipboard Papermaking |
Service advantages | Foreign import, goods preparation and supply | Reasonable price and reliable quality | Pictures are for reference only |
Product features | Primary source of goods, supply by model | After sales guarantee | Chen 1810693-7731 |
A transfer of data over the network is initiated by a write to onboard SDRAM
from the host system. The write can be as simple as a PIO target write, or it can be
due to a DMA cycle by the resident DMA engine.
While the write to the SDRAM is occurring, circuitry on the RFM‐5565
IS200TSVCH1A automatically writes the data and other pertinent information into the transmit
FIFO. From the transmit FIFO, the transmit circuit retrieves the data and puts it
into a variable length packet of 4 to 64 bytes that is transmitted over the fiber‐optic
interface to the receiver of the next board.
The receiver then checks the packet for errors. When the error free data is
received, the receive circuit opens the packet and stores the data in the board’s
receive FIFO. From the receive FIFO, another circuit writes the data into the local
onboard SDRAM at the same relative location in memory as the originating node.
This circuit also simultaneously routes the data into the board’s own transmit
FIFO. From there, the process is repeated until the data returns to the receiver of
the originating node. At the originating node, the data packet is removed from the
network.
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