Description
GE General Electric Technical Specifications: IS200TTPWH1A
The PCI IS200TTPWH1A Configuration registers are located in 256 bytes of the PCI Configuration
Space, which follows a template defined by the PCI Specification v2.2. The first
64 bytes of the PCI Configuration Space are composed of a fully predefined
header. Within that header region, each device implements only the necessary
and relevant registers. However, all registers and bit functions within the header
IS200TTPWH1A region, that are present, must comply with the definitions of the PCI Specification.
Beyond the first 64 byte boundary, each device can implement additional device
unique registers. Although the PCI Configuration registers are accessible at all
times, they are rarely altered by the user.
| brand | Product Name | Product model | Order No |
| GE Fanuc | Module card | IS200TTPWH1A | nothing |
| Place of Origin | Marketable land | Imported or not | defects liability period |
| Europe and America | Nationwide and overseas | yes | a year |
| Place of shipment | Delivery method | How to use | Applicable industries |
| Xiamen | Shunfeng Express | Commissioning and installation | Power Plant Steel Plant Cement Plant Shipboard Papermaking |
| Service advantages | Foreign import, goods preparation and supply | Reasonable price and reliable quality | Pictures are for reference only |
| Product features | Primary source of goods, supply by model | After sales guarantee | Chen 1810693-7731 |
The IS200TTPWH1A contains a number of sources for the interrupt. The second tier of
interrupts is controlled by two registers called the LISR as shown in Table 3‐44 on
page 52 and the LIER shown in Table 3‐45 on page 55. All Local Interrupts are
logically “ORed” together into the single interrupt called the LINTi#. The LINTi#
line is, in turn, controlled by Bit 11 of the Local Configuration register (INTCSR at
offset $68 to Base address 0). The control and status of local interrupts are
implemented in the two local registers (LISR and LIER). The bit functions of these
two registers mirror each other.
IS200TTPWH1A Local Interrupt Status Register
Local Interrupt Status Register (LISR) BAR2 (Offset $10): This is a 32‐bit register
containing a group of interrupt status flags. The LIER contains a corresponding
group of enables. Before any local interrupt can cause an interrupt on the LINTi#
line, the Status Bit, its Enable and the Global Enable must be asserted.
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