GE IS200TVBAH2A Gas turbine card

Description

GE General Electric Technical Specifications: IS200TVBAH2A

In summary, register LAS1RR is the range register corresponding to the size of the

IS200TVBAH2A PCI window and is read‐only. Register LAS1BA is the writeable base address

register. It is used to remap or offset the PCI PIO window to access other sections

of the installed memory. The RFM‐5565 firmware prevents the user from entering

an invalid Remap Value. The value written must be a multiple of the PCI window

size. For example, using a PCI window size of 2 MByte with 64 MByte of installed

IS200TVBAH2A memory means there are 32 valid base address settings from $00000000 to

$03E00000, incrementing by $00200000 (all other bits are masked off when

written). Also, a 64 MByte card with a 64 MByte window has no valid base

address settings other than the default 0.

Since the PCI window size and the Remap register only affect PCI PIO accesses,

DMA (Local‐to‐PCI and PCI‐to‐Local) can be used normally to transfer up to

$7FFFFF bytes with another location on the PCI bus regardless of the Remap

value.

The following is an example of the steps necessary to set up the RFM‐5565 to

generate a PCI interrupt in response to one of the four basic network interrupts.

This example also lists the steps necessary to service that interrupt. When using

this example, it is advisable to examine Figure 2‐1 on page 28 and Figure 3‐1 on

page 58 to obtain a visual sense of the circuitry involved.

IS200TVBAH2A Setup

1. Clear any prior unscheduled interrupts in the SID1 FIFO by writing zero (0)

to the SID1 at PCIBAR2 + offset $24.

2. Clear any prior unscheduled interrupts in the SID2 FIFO by writing zero (0)

to the SID2 at PCIBAR2 + offset $2C.

3. Clear any prior unscheduled interrupts in the SID3 FIFO by writing zero (0)

to the SID3 at PCIBAR2 + offset $34.

4. Clear any prior unscheduled interrupts in the SID4 FIFO by writing zero (0)

to the SID4 at PCIBAR2 + offset $3C.

5. Using a read‐modify‐write operation, set Bit 07, Bit 02, Bit 01 and Bit 00 high

(1) in the LIER register at PCIBAR2 + offset $14. This allows any one of the

four basic network interrupts to assert the onboard signal LINTi#, provided

the global enable in the LISR is also high (1).

6. IS200TVBAH2A Write the value $4000 to the LISR register at PCIBAR2 + offset $10. The value

$4000 sets the Global Interrupt Enable (Bit 14) high (1) and clears any unre‐

lated sources. You may prefer to use a read‐modify‐write operation if other

sources in the LISR are to remain unchanged.

7. Using a read‐modify‐write operation, set Bit 8 and Bit 11 high (1) in the

INTCSR register at PCIBAR0 + offset $68. Bit 8 is the PCI Interrupt Enable

and Bit 11 is the Local Interrupt Input (LINTi#) Enable.

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