HIMA F8621A Digital Output Board

Description

F8621A The 5 V DC power needed for the microprocessor system and as control

current for the I/O modules is generated from the 24 V DC power of the

system via clocked 24 V DC / 5 V DC power supply modules bearing the

F 7126 identification. One central rack can be equipped with a maximum

of 3 power supply modules. F8621A The power supply modules are switched in

parallel. One or two power supply modules are usually able to supply the

PES. A further power supply module is used to increase availability.

The output voltage of the power supply modules is checked as to under

voltage and failure by a monitoring module F 7131.

In case of a faulty power supply module the operating system supplies the

user’s program via a system variable with this information.

In case the 5 V DC system power fails F8621A hardware clock and sRAM on the

central module are buffered by one lithium battery on the central module.

Two lithium batteries on the power supply monitoring module F 7131 are

to buffer the sRAM on the coprocessor module.

F8621A The data connection of the I/O level with the central device is established

via the I/O bus. The I/O bus coupling modules are already integrated in the

central rack. A data cable BV 7032 is used to connect the I/O bus between

central module 1 (XD.2) and central module 2 (XD.1).

With the I/O subrack the connection to the I/O F8621A bus is via a coupling module

F 7553 installed in slot 17. The connection of the bus between the indivi

dual subracks is established at the rear side via the BV 7032 data cable.

In case of an error the plant is to be driven in the safe state. For systems

with a defined safety state this is the lowest energetic state. According to

the defined reaction on faults during operation (refer to the table in chapter

4.1) different levels of shut down are executed.

These essential functions are

– two clock-synchronised micro processors

– each mikroprocessor with an own data area, one processor operates

F8621A with real data and program and the other one with inverted data and

program

– testable hardware comparer for all the external accesses of both micro

processors, in case of a fault the watch dog will be set to the safe sta

tus and the status of the processor is announced

– Flash-EPROMs of the program memory for the operating system and

F8621A the user’s program usable for min. 100.000 writing cycles

– Data memory in sRAM

– Multiplexer to connect I/O bus, DPR and redundant CU

– Battery backup of the sRAMs via batteries on the central module with

monitoring

– 2 interfaces RS 485 with galvanic isolation. Transm. rate: max. 57600

bps. Set to 9600 bps and to 57600 bps by switch, or setting also of

other transm. rates by software (the software values have priority)

– Diagnostic display and 2 LEDs for information out of the system, I/O

level and user’s program

– Dual Port RAM for fast memory access to the second central module

– hardware clock, battery backed

– I/O bus logic and connection to the input-/output modules

– Fail-safe watchdog

– power supply monitoring, testable (5 V system voltage)

– Battery monitoring

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