Description
The 5V DC power supply does not have to be wired separately as it is already installed as part of the subrack.
The 5 V DC power is needed by the CPU, the control of the interfaces, and the I/O modules. It is generated by a clocked 24 V DC/5 V DC power supply module bearing the F 7130A identification. The subrack is equipped with two power supply modules. The power supply modules are paralleled. If one of them fails, the other supplies the PES.
The 5 V DC output voltage of the power supply modules (for the CPU, I/ O, and the interfaces) are monitored on the central unit checking undervoltage and failure.
In case of a faulty power supply module the operating system supplies the user’s program via a system variable with this information.
In case the 5 V DC system power fails hardware clock and RAM on the central module are buffered by a lithium battery which is also on the central unit.
| brand | Product Name | Product model | Order No |
| HIMA | modular | H51q-HS B5233-1 997105233 | nothing |
| Place of Origin | Marketable land | Imported or not | defects liability period |
| Europe and America | Nationwide and overseas | yes | a year |
| Place of shipment | Delivery method | How to use | Applicable industries |
| Xiamen | Shunfeng Express | Commissioning and installation | Power Plant Steel Plant Cement Plant Shipboard Papermaking |
| Service advantages | Foreign import, goods preparation and supply | Reasonable price and reliable quality | Pictures are for reference only |
| Product features | Primary source of goods, supply by model | After sales guarantee | Chen 1810693-7731 |
– two clock-synchronised micro processors
– each mikroprocessor with an own memory, one processor operates with real data and program and the other one with inverted data and program – testable hardware comparer for all the external accesses of both micro processors, in case of a fault the watch dog will be set to the safe state and the status of the processor is announced
– Flash-EPROMs of the program memory for the operating system and the user’s program usable for min. 100.000 writing cycles
– Data memory in sRAM – Multiplexer to connect I/O bus, DPR and redundant CU
– Battery backup of the sRAMs via batteries on the central module with monitoring and on the bus board
– 2 interfaces RS 485 with galvanic isolation. Transm. rate: max. 57600 bps. Set to 9600 bps and to 57600 bps by switch, or setting also of other transm. rates by software (the software values have priority)
– Diagnostic display and 2 LEDs for information out of the system, I/O level and project
– Dual Port RAM for fast memory access to the second central module
– hardware clock, battery backed
– I/O bus logic and connection to the input-/output modules
– Fail-safe watchdog
– power supply monitoring, testable (5 V system voltage)
– Battery monitoring
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