NI PXI-6542 waveform storage device

NI PXI-6542 waveform storage device

These specifications apply to the PXI-6542 with 1 MBit, 8 MBit, and 64 MBit of memory per channel. Hot Surface If the PXI-6542 has been in use, it may exceed safe handling temperatures and cause burns. Allow the PXI-6542 to cool before removing it from the chassis. Note All values were obtained using a 1 m cable (SHC68-C68-D4 recommended). Performance specifications are not guaranteed when using longer cables.

Channels
Data
Number of channels 32
Direction control Per channel
Programmable Function Interface (PFI)
Number of channels 4
Direction control Per channel
Clock terminals
Input 3
Output 2

Maximum DC drive strength, by logic family
1.8 V ±8 mA
2.5 V ±16 mA
3.3 V ±32 mA
Data channel driver enable/disable control Software-selectable: per channel
Channel power-on state1 Drivers disabled, 50 kΩ input impedance
Output protection
Range 0 V to 5 V
Duration Indefinite

Generation Timing
Channels Data
DDC CLK OUT
PFI <0..3>
Data channel-to-channel skew ±600 ps, typical
Maximum data channel toggle rate 50 MHz
Data position modes Sample clock rising edge
Sample clock falling edge
Delay from Sample clock rising edge
Generation data delay (δG), for clock frequencies ≥25 MHz
Range 0.0 to 1.0 Sample clock periods
Resolution 1/256 of Sample clock period
Exported Sample clock offset (tCO) Software-selectable: 0.0 ns or 2.5 ns (default)
Time delay from Sample clock (internal)
to DDC connector (tSCDDC)
15 ns, typical

Title: Optimizing Signal Timing for PXI-6542 Generation Sessions

Introduction: Ensuring precise signal timing is crucial for PXI-6542 generation sessions. This article provides insights into configuring the exported Sample clock mode and offset for optimal performance. It covers considerations such as data position, clock edge, and worst-case effects like channel-to-channel skew, inter-symbol interference, and jitter.

Understanding Table Values: The table values assume a Sample clock rising edge with export to the DDC connector. These values encompass worst-case scenarios, including channel effects. Users can explore different combinations of Sample clock modes and offsets, providing flexibility in configuration.

Default and Balanced Configurations: The default case features a noninverted clock with a 2.5 s offset, while a balanced setup employs an inverted clock with a 0 ns offset. These configurations aim to address specific timing challenges, ensuring reliability in data transmission.

Choosing the Right Configuration: To determine the optimal exported Sample clock mode and offset for your PXI-6542 generation session, compare setup and hold times with the datasheet of your device under test (DUT). Select configurations where the PXI-6542 setup and hold times surpass those required for the DUT.

Considerations for Specified Timing: Timing relationships specified at the DDC connector and high-speed DIO accessory terminals are critical. Various factors, such as signal routing, clock splitting, buffers, or translation logic, can impact these relationships. For applications requiring multiple DDC_CLK_OUT copies, using a zero buffer is recommended to maintain timing integrity.

Conclusion: Achieving precise signal timing in PXI-6542 generation sessions is essential for reliable data transmission. By carefully selecting the exported Sample clock mode and offset based on setup and hold time comparisons, users can optimize performance for their specific device under test. Additionally, understanding and mitigating potential impacts of signal routing and buffering further contribute to maintaining accurate timing relationships.